Intel L3-cache slice partitioning visualisation

physical addr

architecture Sandy Bridge Haswell #cores 2 4 8 'x delta' 0x40 (cache line) 0x80 0x100 0x200 0x400 0x800 0x1000 (page) 0x2000 0x4000 0x8000 0x10000 0x20000 (cache set) 'y delta' 0x1000 (page) 0x2000 0x4000 0x8000 0x10000 0x20000 (cache set) 0x40000 0x80000 0x100000 0x200000 0x400000 0x800000

slices: 0 black white red green blue yellow cyan orange 1 black white red green blue yellow cyan orange 2 black white red green blue yellow cyan orange 3 black white red green blue yellow cyan orange 4 black white red green blue yellow cyan orange 5 black white red green blue yellow cyan orange 6 black white red green blue yellow cyan orange 7 black white red green blue yellow cyan orange

hash functions from:

• Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters
• Practical Timing Side Channel Attacks Against Kernel Space ASLR